Patent attributes
A method of designing a layout includes identifying a cell having a cell height being a non-integral multiple of a minimum pitch, generating, using a processor, possibilities of an ordered arrangement of a plurality of virtual grid lines parallel to the top boundary and the bottom boundary, and placing at least two conductive patterns on the plurality of virtual grid lines. The cell height is defined by a top boundary and a bottom boundary, and the minimum pitch is based on a manufacturing process. The plurality of virtual grid lines are separated from each other by a plurality of spacings, and the top boundary overlaps a first virtual grid line of the plurality of virtual grid lines and the bottom boundary overlaps a second virtual grid line of the plurality of virtual grid lines. At least one spacing is different from another spacing of the plurality of spacings.
