Log in
Enquire now
‌

US Patent 11714947 Method and layout of an integrated circuit

OverviewStructured DataIssuesContributors

Contents

Is a
Patent
Patent
0

Patent attributes

Patent Applicant
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
0
Current Assignee
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
117149470
Date of Patent
August 1, 2023
0
Patent Application Number
177502010
Date Filed
May 20, 2022
0
Patent Citations
‌
US Patent 8875076 System and methods for converting planar design to FinFET design
0
‌
US Patent 9147029 Stretch dummy cell insertion in FinFET process
0
‌
US Patent 9501600 Standard cells for predetermined function having different types of layout
0
‌
US Patent 10402529 Method and layout of an integrated circuit
0
‌
US Patent 10936780 Method and layout of an integrated circuit
0
‌
US Patent 11348925 Matching nanowire FET periodic structuire to standard cell periodic structure in integrated circuits
0
‌
US Patent 11341308 Method and layout of an integrated circuit
0
‌
US Patent 8421205 Power layout for integrated circuits
0
...
Patent Primary Examiner
‌
Phallaka Kik
0
CPC Code
‌
G06F 30/3947
0
‌
G06F 30/3953
0
‌
G06F 2119/18
0
‌
G06F 30/392
0
‌
H01L 21/027
0
‌
H01L 21/76895
0
‌
Y02P 90/02
0
‌
G03F 1/36
0
...

A method of manufacturing an integrated circuit includes adjusting a first spacing between an adjacent pair of routing tracks in a first set of routing tracks to be equal to a second spacing, adjusting a third spacing between an adjacent pair of routing tracks in a second set of routing tracks to be equal to a fourth spacing, placing a first and second pair of conductive patterns on the corresponding first and second set of routing tracks, forming a first set of conductive structures based on the first pair of conductive patterns, and a second set of conductive structures based on the second pair of conductive patterns. A first and second cell have a same cell height that is a non-integer multiple of a minimum pitch. One spacing of a first set of spacings is different from another spacing of the first set of spacings.

Timeline

No Timeline data yet.

Further Resources

Title
Author
Link
Type
Date
No Further Resources data yet.

References

Find more entities like US Patent 11714947 Method and layout of an integrated circuit

Use the Golden Query Tool to find similar entities by any field in the Knowledge Graph, including industry, location, and more.
Open Query Tool
Access by API
Golden Query Tool
Golden logo

Company

  • Home
  • Press & Media
  • Blog
  • Careers
  • WE'RE HIRING

Products

  • Knowledge Graph
  • Query Tool
  • Data Requests
  • Knowledge Storage
  • API
  • Pricing
  • Enterprise
  • ChatGPT Plugin

Legal

  • Terms of Service
  • Enterprise Terms of Service
  • Privacy Policy

Help

  • Help center
  • API Documentation
  • Contact Us