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US Patent 11714947 Method and layout of an integrated circuit

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
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Current Assignee
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Date Filed
May 20, 2022
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Date of Patent
August 1, 2023
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Patent Applicant
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Patent Application Number
17750201
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Patent Citations
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US Patent 8875076 System and methods for converting planar design to FinFET design
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US Patent 9147029 Stretch dummy cell insertion in FinFET process
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US Patent 9501600 Standard cells for predetermined function having different types of layout
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US Patent 10402529 Method and layout of an integrated circuit
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US Patent 10936780 Method and layout of an integrated circuit
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US Patent 11348925 Matching nanowire FET periodic structuire to standard cell periodic structure in integrated circuits
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US Patent 11341308 Method and layout of an integrated circuit
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US Patent 8421205 Power layout for integrated circuits
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US Patent 8661389 Systems and methods of designing integrated circuits
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US Patent 8698205 Integrated circuit layout having mixed track standard cell
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•••
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11714947
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Patent Primary Examiner
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Phallaka Kik
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CPC Code
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G06F 30/3947
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G06F 30/3953
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G06F 2119/18
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G06F 30/392
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H01L 21/027
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H01L 21/76895
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Y02P 90/02
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G03F 1/36
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G06F 30/398
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