US Patent 10404470 Signature verification of field-programmable gate array programs

Techniques for signature verification of field-programmable gate array (FPGA) programs are described herein. In one or more implementations, an FPGA virtualization manager of a host device receives a request from a virtual machine for an FPGA program to program FPGAs of the host. The FPGA program is configured to program the FPGAs to provide functionality of a hardware-implementation of a respective program (e.g., a machine-learning algorithm) or of a respective device (e.g., a graphics processing unit). Before allowing the FPGA program to program the FPGAs, however, the FPGA virtualization manager determines whether the FPGA program is trusted to do so. To do so, the FPGA virtualization manager verifies a digital signature associated with the FPGA program. When the signature is verified the FPGA program is determined to be trusted. Based on such a determination, the FPGA virtualization manager loads the FPGA program to program the FPGAs to provide the functionality.