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US Patent 10411720 Efficient and dependable clock synchronization in hardware

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Patent attributes

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

Date of Patent

September 10, 2019

Patent Application Number

16006498

Date Filed

June 12, 2018

Patent Citations Received

US Patent 12113539 Field programmable gate array with external phase-locked loop

0

US Patent 11520370 Delay element, delay element chain and fast all-digital clock frequency adaptation circuit for voltage droop tolerance

US Patent 11329655 Field programmable gate array with internal phase-locked loop

US Patent 12107587 Field programmable gate array with internal phase-locked loop

0

US Patent 11502694 Field programmable gate array with external phase-locked loop

US Patent 10621067 Data unit breakpointing circuits and methods

US Patent 10763865 Field programmable gate array with internal phase-locked loop

US Patent 10826502 Field programmable gate array with external phase-locked loop

...

Patent Primary Examiner

Patent abstract

The invention comprises a fault-tolerant clock synchronization method with high precision, hardware implementations thereof and the corresponding digital circuits, designed to contain metastability.

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