US Patent 10431517 Arrangement and thermal management of 3D stacked dies
Patent 10431517 was granted and assigned to Advanced Micro Devices on October, 2019 by the United States Patent and Trademark Office.
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Patent abstract
Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.
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Patent Inventor Names
Brett P. Wilkerson0
John Wuu0
Kaushik Mysore0
Milind S. Bhagavat0
Patrick J. Shyvers0
Samuel Naffziger0
Edits on 7 Apr, 2023
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Infobox
Is a
Current Assignee
Patent Jurisdiction
Patent Number
104315170
Date of Patent
October 1, 2019
0Patent Application Number
156865580
Date Filed
August 25, 2017
0Patent Citations Received
Patent Primary Examiner
Edits on 10 Feb, 2022
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Patent citations received
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US Patent 10431517 Arrangement and thermal management of 3D stacked dies
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
10431517
Date of patent
October 1, 2019
Patent application number
15686558
Date Filed
August 25, 2017
Patent primary examiner
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