US Patent 10460813 Nonvolatile memory devices providing reduced data line load

A nonvolatile memory device according to some embodiments of the inventive concepts may include a memory cell array, a first page buffer connected to the memory cell array via a first plurality of bit lines, and a second page buffer connected to the memory cell array via a second plurality of bit lines. The first page buffer circuit may include a first bit line selection circuit, a first bit line shut-off circuit, and a first latch circuit. The second page buffer may include a second bit line selection circuit, a second bit line shut-off circuit, and a second latch circuit. The first and second bit line selection circuits, the first and second bit line shut-off circuits, and the first and second latch circuits may be sequentially arranged in a direction away from the memory cell array. A width of the data lines may be greater than a width of the bit lines.