US Patent 10491365 Clock-data recovery circuit with metastability detection and resolution

Apparatus(es) and method(s) for CDR are described. In a CDR circuit, there is a bang-bang phase detector (“BBPD”), a baud-rate phase detector (“BRPD”), a multiplexer, and a control circuit. The BBPD, configured to receive data and crossing samples, generates a first result indicating a first phase difference between data and crossing samples. The BRPD, configured to receive data and peak samples, generates a second result indicating a second phase difference between data and peak samples. The multiplexer is configured to select either such result as a phase-detect output for a mode of operation. A control circuit is configured to clear a metastable state: for receipt of the first detect result, check for dithering, determine a direction for phase adjustment responsive to detection of the dithering, and provide a phase adjustment in the direction; and for receipt of the second detect result, operate to use the second phase difference generated.