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US Patent 10491365 Clock-data recovery circuit with metastability detection and resolution

Patent 10491365 was granted and assigned to Xilinx on November, 2019 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
Current Assignee
Xilinx
Xilinx
Date Filed
October 24, 2018
Date of Patent
November 26, 2019
Patent Applicant
Xilinx
Xilinx
Patent Application Number
16169719
Patent Citations Received
‌
US Patent 11496282 Horizontal centering of sampling point using vertical vernier
‌
US Patent 11522551 PLL jitter detection
‌
US Patent 11757681 Serial data receiver circuit with dither assisted equalization
‌
US Patent 11804992 Asymetric decision feedback equalization
‌
US Patent 11374800 Continuous time linear equalization and bandwidth adaptation using peak detector
0
‌
US Patent 11838156 Continuous time linear equalization and bandwidth adaptation using asynchronous sampling
0
‌
US Patent 10749664 Clock data recovery for automotive vision system
0
‌
US Patent 11563605 Horizontal centering of sampling point using multiple vertical voltage measurements
‌
US Patent 10911035 Fixed-width pulse generator
0
‌
US Patent 11303484 Continuous time linear equalization and bandwidth adaptation using asynchronous sampling
0
Patent Inventor Names
Winson Lin
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10491365
Patent Primary Examiner
‌
Daniel C Puentes

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