US Patent 10505555 Crystal oscillator offset trim in a phase-locked loop

A phase-locked loop (PLL) includes a time-to-digital converter (TDC) to receive a reference clock. The PLL also includes a digital loop filter coupled to the TDC. The digital loop filter repeatedly generates frequency control words. An analog phase-locked loop (APLL) includes a programmable frequency divider. A non-volatile memory device stores a value from the digital loop filter. The PLL includes a free-run control circuit. Upon a power-on reset process, the free-run circuit retrieves the value from the non-volatile memory to adjust a divide ratio of the programmable frequency divider based on the retrieved value. Upon a reference clock provided to the TDC, the free-run control circuit continues to adjust the divide ratio of the programmable frequency divider based on both the retrieved value from the non-volatile memory and a current frequency control word from the digital loop filter.