US Patent 10510649 Interconnect substrate

An interconnect substrate includes an insulating layer having a first resin layer and a second resin layer covering an upper surface of the first resin layer, a first conductive layer having an upper surface and side surfaces covered with the first resin layer, a lower surface of the first conductive layer being exposed from a lower surface of the first resin layer, and a second conductive layer including an interconnect pattern and a via interconnect, the interconnect pattern being disposed on an upper surface of the second resin layer, the via interconnect penetrating through both the second resin layer and the first resin layer to connect the interconnect pattern to the upper surface of the first conductive layer, wherein the first resin layer is made of a resin having a higher modulus of elasticity and a lower coefficient of elongation than the second resin layer.