US Patent 10515886 Scalable semiconductor interposer integration

An electronic package comprising a first substrate; a second substrate; at least one standoff substrate positioned between the first substrate and the second substrate, wherein the at least one standoff substrate is affixed to each of the first substrate and the second substrate, wherein the at least one standoff substrate forms a clearance between the first substrate and the second substrate, and wherein the at least one standoff substrate comprises an intervening plurality of through-substrate vias passing through the entire thickness of the at least one standoff substrate, and wherein a portion of the second plurality of through-substrate vias are electrically connected to a portion of the first through-substrate vias by way of a portion of the intervening through-substrate vias; and at least three electronic components located within the clearance.