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US Patent 10516064 Multiple width nanosheet devices

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
August 14, 2018
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Date of Patent
December 24, 2019
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Patent Application Number
16103283
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Patent Citations Received
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US Patent 12002850 Nanosheet-based semiconductor structure with dielectric pillar
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US Patent 11322496 Method for making field effect transistor and field effect transistor formed
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US Patent 11764263 Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches
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US Patent 11769836 Gate-all-around integrated circuit structures having nanowires with tight vertical spacing
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US Patent 11430892 Inner spacers for gate-all-around transistors
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US Patent 11855216 Inner spacers for gate-all-around transistors
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US Patent 11527612 Gate-all-around integrated circuit structures having vertically discrete source or drain structures
Patent Inventor Names
Carl Radens
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John H. Zhang
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Junli Wang
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Kangguo Cheng
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Lawrence A. Clevenger
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10516064
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Patent Primary Examiner
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Yasser A Abdelaziez
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