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US Patent 10522213 Memory device comprising an electrically floating body transistor

Patent 10522213 was granted and assigned to Zeno Semiconductor on December, 2019 by the United States Patent and Trademark Office.

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Is a

Patent attributes

Patent Applicant

Zeno Semiconductor

Current Assignee

Zeno Semiconductor

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

Date of Patent

December 31, 2019

Patent Application Number

16170928

Date Filed

October 25, 2018

Patent Citations

US Patent 10056387 Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

US Patent 10074653 Asymmetric semiconductor memory device having electrically floating body transistor

US Patent 10079236 Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor

US Patent 10103148 NAND string utilizing floating body memory cell

US Patent 10109349 Memory cells, memory cell arrays, methods of using and methods of making

US Patent 10103149 Memory device comprising electrically floating body transistor

US Patent 10141046 Memory device comprising an electrically floating body transistor

US Patent 10008266 Semiconductor device having electrically floating body transistor, semiconductor device having both volatile and non-volatile functionality and method of operating

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Patent Citations Received

US Patent 12094526 Memory device comprising electrically floating body transistor

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US Patent 11943937 Memory cell and memory array select transistor

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US Patent 11489073 Memory device comprising an electrically floating body transistor and methods of operating

US Patent 10854745 Memory device comprising an electrically floating body transistor and methods of using

US Patent 10916297 Memory device comprising an electrically floating body transistor

US Patent 10923183 Memory device comprising electrically floating body transistor

US Patent 11600663 Memory cell and memory array select transistor

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Patent Primary Examiner

Allison Bernstein

Patent abstract

A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.

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