Patent attributes
A circuit and corresponding method enable glitch-free frequency. The circuit comprises a first delay circuit and a second delay circuit, configured to produce first and second propagated enables, respectively, from first and second input enables, respectively; and an output clock circuit. The output clock circuit is configured to produce an output clock that switches, glitch-free, between a first phase-locked clock and a second phase-locked. The first and second delay circuits are further configured to enable the output clock to be switched, glitch-free, by employing the second propagated enable to gate propagation of the first input enable and the first propagated enable to gate propagation of the second input enable, respectively. The first and second input enables are configured to be enabled, alternately, causing the output clock to switch between the first and second phase-locked clocks.
