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US Patent 10530370 Glitch-free PLL Multiplexer

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
December 4, 2018
Date of Patent
January 7, 2020
Patent Application Number
16209709
Patent Citations Received
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US Patent 11927612 Digital droop detector
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US Patent 11545981 DLL-based clocking architecture with programmable delay at phase detector inputs
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US Patent 11545987 Traversing a variable delay line in a deterministic number of clock cycles
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US Patent 10784871 Clocking architecture for DVFS with low-frequency DLL locking
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US Patent 11803207 Reference independent and noise insensitive glitch free clock multiplexer
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US Patent 11402413 Droop detection and mitigation
Patent Inventor Names
Georgios Faldamis
0
Nitin Mohan
0
Thucydides Xanthopoulos
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10530370
Patent Primary Examiner
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Daniel C Puentes

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