US Patent 10546830 Chip package structure

A chip package structure is provided. The chip package structure includes a first redistribution structure including a dielectric structure and a plurality of wiring layers in the dielectric structure. The chip package structure includes a first chip over the first surface. The chip package structure includes a first conductive bump between the first chip and the first redistribution structure. The chip package structure includes a first conductive pillar over the first surface adjacent to the first chip and electrically connected to the wiring layers. The chip package structure includes a second chip over the second surface. The chip package structure includes a second conductive pillar over the second surface adjacent to the second chip and electrically connected to the wiring layers. The chip package structure includes a first molding layer over the first surface and surrounding the first chip, the first conductive bump, and the first conductive pillar.