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US Patent 10585996 Die resistance-capacitance extraction and validation

Patent 10585996 was granted and assigned to Seagate Technology on March, 2020 by the United States Patent and Trademark Office.

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Patent abstract

Systems and methods for die resistance-capacitance (RC) extraction and validation are described. In one embodiment, the method includes generating a chip power model (CPM) based at least in part on single domain excitation to determine a die capacitance; and performing loop-based static IR drop analysis to determine a die resistance for each power domain of a die. In some cases, the generating of the chip power model (CPM) includes generating a separate CPM for each power domain of the die.

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Patent Inventor Names
Nitin Kumar Chhabra0
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Patent Citations Received
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US Patent 11663388 DVD simulation using microcircuits
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Patent Citations Received
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US Patent 11531794 Voltage drop analysis using local circuit representation
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Infobox
Is a
Patent
Patent
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Patent Applicant
Seagate Technology
Seagate Technology
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Current Assignee
Seagate Technology
Seagate Technology
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
105859960
Date of Patent
March 10, 2020
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Patent Application Number
158695420
Date Filed
January 12, 2018
0
Patent Citations Received
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US Patent 10990731 Dynamic voltage drop analysis with improved coverage
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Patent Primary Examiner
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Bryce M Aisaka
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US Patent 10990731 Dynamic voltage drop analysis with improved coverage
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 US Patent 10585996 Die resistance-capacitance extraction and validation

Infobox
Is a
Patent
Patent
Patent applicant
Seagate Technology
Seagate Technology
Current assignee
Seagate Technology
Seagate Technology
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
10585996
Date of patent
March 10, 2020
Patent application number
15869542
Date Filed
January 12, 2018
Patent primary examiner
‌
Bryce M Aisaka

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