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US Patent 10615257 Patterning method for nanosheet transistors

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Patent Citations Received
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US Patent 11664656 ESD protection for integrated circuit devices
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Infobox
Is a
Patent
Patent
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
106152570
Date of Patent
April 7, 2020
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Patent Application Number
161248730
Date Filed
September 7, 2018
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Patent Citations
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US Patent 10038053 Methods for removal of selected nanowires in stacked gate all around architecture
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US Patent 10103063 Forming a hybrid channel nanosheet semiconductor structure
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US Patent 10103065 Gate metal patterning for tight pitch applications
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US Patent 10249541 Forming a hybrid channel nanosheet semiconductor structure
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US Patent 10276452 Low undercut N-P work function metal patterning in nanosheet replacement metal gate process
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US Patent 10304936 Protection of high-K dielectric during reliability anneal on nanosheet structures
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US Patent 10332803 Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming
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US Patent 10332809 Method and structure to introduce strain in stack nanosheet field effect transistor
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US Patent 10374034 Undercut control in isotropic wet etch processes
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US Patent 10388577 Nanosheet devices with different types of work function metals
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US Patent 10410933 Replacement metal gate patterning for nanosheet devices
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Patent Citations Received
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US Patent 11368016 ESD protection for integrated circuit devices
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US Patent 11387319 Nanosheet transistor device with bottom isolation
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Patent Primary Examiner
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Victoria K. Hall
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Patent citations received
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US Patent 11387319 Nanosheet transistor device with bottom isolation
Edits on 22 Jun, 2022
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edited on 22 Jun, 2022
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Patent citations received
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US Patent 11368016 ESD protection for integrated circuit devices

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