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US Patent 10636498 Managing bit-line settling time in non-volatile memory

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
February 22, 2019
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Date of Patent
April 28, 2020
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Patent Application Number
16283441
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Patent Citations
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US Patent 10157680 Sub-block mode for non-volatile memory
Patent Citations Received
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US Patent 11972815 Post-write read techniques to improve programming reliability in a memory device
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US Patent 11705190 Method of programming memory device and related memory device
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US Patent 11367491 Technique for adjusting read timing parameters for read error handling
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US Patent 11804268 Methods of operating memory devices based on sub-block positions and related memory system
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US Patent 10971235 Methods of operating memory devices based on sub-block positions and related memory system
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US Patent 11024371 Method of programming memory device and related memory device
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US Patent 11621045 Non volatile flash memory with improved verification recovery and column seeding
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US Patent 11276465 Device, system and method to float a decoder for deselected address lines in a three-dimensional crosspoint memory architecture
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US Patent 11276471 Methods of operating memory devices based on sub-block positions and related memory system
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10636498
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Patent Primary Examiner
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Gene N Auduong
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