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US Patent 10643011 Automatic design and verification of safety critical electronic systems

Patent 10643011 was granted and assigned to Cadence Design Systems on May, 2020 by the United States Patent and Trademark Office.

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Patent Applicant

Cadence Design Systems

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Current Assignee

Cadence Design Systems

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Patent Jurisdiction

United States Patent and Trademark Office

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Patent Number

Date of Patent

May 5, 2020

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Patent Application Number

160239370

Date Filed

June 29, 2018

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Patent Citations Received

US Patent 12124789 Multi-stage electronic design automation parameter tuning

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US Patent 11709767 Method and apparatus for verifying operation state of application

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US Patent 11422185 System and method for testing critical components on system-on-chip

US Patent 11842134 Automated determinaton of failure mode distribution

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US Patent 11550979 Implementing and verifying safety measures in a system design based on safety specification generated from safety requirements

US Patent 10853545 Automatic gate-level FS analysis and FMEDA

US Patent 11042688 Method of certifying safety levels of semiconductor memories in integrated circuits

US Patent 11630938 Failure mode analysis for circuit design

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