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US Patent 10672744 3D compute circuit with high density Z-axis interconnects

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Patent Citations Received
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US Patent 12027512 Chipset and manufacturing method thereof
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US Patent 11790219 Three dimensional circuit implementing machine trained network
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=1067274400
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Patent Citations Received
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US Patent 11270979 Symbiotic network on layers
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Infobox
Is a
Patent
Patent
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
106727440
Date of Patent
June 2, 2020
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Patent Application Number
161597040
Date Filed
October 14, 2018
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=106727440
Patent Citations
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US Patent 10121743 Power distribution networks for a three-dimensional (3D) integrated circuit (IC) (3DIC)
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US Patent 10255969 Multi channel semiconductor device having multi dies and operation method thereof
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US Patent 10262911 Circuit for and method of testing bond connections between a first die and a second die
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US Patent 10269586 Package structure and methods of forming same
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US Patent 10373657 Semiconductor layered device with data bus
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US Patent 10446207 Spin transfer torque magnetic random access memory for supporting operational modes with mode register
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US Patent 10446601 Photodetector
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US Patent 10580817 Photodetector
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Patent Citations Received
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US Patent 10886177 3D chip with shared clock distribution network
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US Patent 10892252 Face-to-face mounted IC dies with orthogonal top interconnect layers
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US Patent 10950547 Stacked IC structure with system level wiring on multiple sides of the IC die
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US Patent 10970627 Time borrowing between layers of a three dimensional chip stack
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US Patent 10978348 3D chip sharing power interconnect layer
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US Patent 11264361 Network on layer enabled architectures
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US Patent 11270979 Symbiotic network on layers
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US Patent 11289333 Direct-bonded native interconnects and active base die
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US Patent 11557516 3D chip with shared clock distribution network
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US Patent 11599299 3D memory circuit
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Patent Primary Examiner
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Ida M. Soward
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US Patent 11599299 3D memory circuit
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Patent Citations Received
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US Patent 11557516 3D chip with shared clock distribution network
0
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