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US Patent 10672744 3D compute circuit with high density Z-axis interconnects
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Patent
Date Filed
October 14, 2018
Date of Patent
June 2, 2020
Patent Application Number
16159704
Patent Citations
US Patent 10262911 Circuit for and method of testing bond connections between a first die and a second die
US Patent 10269586 Package structure and methods of forming same
US Patent 10373657 Semiconductor layered device with data bus
US Patent 10446601 Photodetector
US Patent 10446207 Spin transfer torque magnetic random access memory for supporting operational modes with mode register
US Patent 10580817 Photodetector
US Patent 10121743 Power distribution networks for a three-dimensional (3D) integrated circuit (IC) (3DIC)
US Patent 10255969 Multi channel semiconductor device having multi dies and operation method thereof
Patent Citations Received
US Patent 12027512 Chipset and manufacturing method thereof
0
US Patent 11270979 Symbiotic network on layers
US Patent 11289333 Direct-bonded native interconnects and active base die
US Patent 11790219 Three dimensional circuit implementing machine trained network
US Patent 11557516 3D chip with shared clock distribution network
US Patent 10886177 3D chip with shared clock distribution network
US Patent 10892252 Face-to-face mounted IC dies with orthogonal top interconnect layers
US Patent 10950547 Stacked IC structure with system level wiring on multiple sides of the IC die
US Patent 10970627 Time borrowing between layers of a three dimensional chip stack
US Patent 10978348 3D chip sharing power interconnect layer
•••
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10672744
Patent Primary Examiner
Ida M. Soward
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