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US Patent 10777468 Stacked vertical field-effect transistors with sacrificial layer patterning

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Patent Citations Received
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US Patent 12029026 Method of manufacturing semiconductor structure and semiconductor structure
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=1077746800
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Infobox
Is a
Patent
Patent
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
107774680
Date of Patent
September 15, 2020
0
Patent Application Number
163603530
Date Filed
March 21, 2019
0
Official Website
https://pdfpiw.uspto.gov/.piw?Docid=107774680
Patent Citations
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US Patent 10157794 Integrated circuit structure with stepped epitaxial region
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US Patent 10361315 Method and apparatus of fabricating source and drain epitaxy for vertical field effect transistor
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US Patent 10468525 VFET CMOS dual epitaxy integration
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Patent Citations Received
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US Patent 11417737 Semiconductor structure having vertical fin with oxidized sidewall and method of manufacturing the same
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US Patent 11588029 Method of manufacturing semiconductor structure having vertical fin with oxidized sidewall
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Patent Primary Examiner
Bradley Smith
Bradley Smith
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 US Patent 10777468 Stacked vertical field-effect transistors with sacrificial layer patterning

Infobox
Is a
Patent
Patent
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
10777468
Date of patent
September 15, 2020
Patent application number
16360353
Date Filed
March 21, 2019
Patent citations
‌
US Patent 10157794 Integrated circuit structure with stepped epitaxial region
‌
US Patent 10361315 Method and apparatus of fabricating source and drain epitaxy for vertical field effect transistor
‌
US Patent 10468525 VFET CMOS dual epitaxy integration
Patent primary examiner
Bradley Smith
Bradley Smith

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