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US Patent 10886177 3D chip with shared clock distribution network

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
June 1, 2020
Date of Patent
January 5, 2021
Patent Application Number
16889698
Patent Citations
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US Patent 10672744 3D compute circuit with high density Z-axis interconnects
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US Patent 10121743 Power distribution networks for a three-dimensional (3D) integrated circuit (IC) (3DIC)
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US Patent 10255969 Multi channel semiconductor device having multi dies and operation method thereof
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US Patent 10262911 Circuit for and method of testing bond connections between a first die and a second die
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US Patent 10269586 Package structure and methods of forming same
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US Patent 10289604 Memory processing core architecture
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US Patent 10373657 Semiconductor layered device with data bus
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US Patent 10446207 Spin transfer torque magnetic random access memory for supporting operational modes with mode register
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US Patent 10446601 Photodetector
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US Patent 10580735 Stacked IC structure with system level wiring on multiple sides of the IC die
•••
Patent Citations Received
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US Patent 12136605 Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics and method for forming the same
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US Patent 11518232 Cone element acting as a clutch in a K0 installation space
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US Patent 11524565 Cone element acting as a clutch in a K0 installation space
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US Patent 12125784 Interconnect structures
0
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US Patent 12132020 Low temperature bonded structures
0
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US Patent 11485218 Cone element acting as a clutch in a K0 installation space
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US Patent 11621246 Diffused bitline replacement in stacked wafer memory
0
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US Patent 11626363 Bonded structures with integrated passive component
0
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US Patent 11631586 Heterogeneous annealing method
0
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US Patent 11631647 Integrated device packages with integrated device die and dummy element
0
•••
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10886177
Patent Primary Examiner
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Brook Kebede

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