US Patent 10892016 3D memory semiconductor devices and structures

A method to operate a 3D semiconductor charge trap memory device, the method comprising; executing a memory set-up operation, wherein said memory set-up operation comprises a preload of a plurality of memory cells followed by a partial erase; and then executing a memory operation on said memory cells, wherein each memory cell of said plurality of memory cells comprises a charge trap layer, wherein said memory operation comprises first writing a first memory state by loading a charge into said charge trap layer, and then second writing a second memory state by removing said charge to a partially erased state. Various 3D devices, processing flows and methods are also disclosed.