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US Patent 10892763 Second-order clock recovery using three feedback paths

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
May 14, 2020
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Date of Patent
January 12, 2021
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Patent Application Number
16874261
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Patent Citations
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US Patent 10211994 Power supply system, power sourcing equipment, and Ethernet Y cable
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US Patent 10305495 Phase control of clock signal based on feedback
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US Patent 10313105 Fractional-N PLL based clock recovery for SerDes
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US Patent 10313165 Finite impulse response analog receive filter with amplifier-based delay chain
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US Patent 10389515 Integrated circuit, multi-channel transmission apparatus and signal transmission method thereof
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US Patent 10447509 Precompensator-based quantization for clock recovery
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US Patent 10447461 Accessing data via different clocks
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US Patent 10727786 Multiport inductors for enhanced signal distribution
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US Patent 10483910 Multiport inductors for enhanced signal distribution
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US Patent 10084623 Multichannel CDR with sharing of adaptation hints and learning
Patent Citations Received
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US Patent 11962676 Phase mixer non-linearity compensation within clock and data recovery circuitry
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US Patent 11671237 Data driving device and method for driving the same
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US Patent 11784855 Adaptive receiver with pre-cursor cancelation
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US Patent 11791826 Clock recovery circuit for display
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US Patent 11936538 Phase-shifted sampling module and method for determining filter coefficients
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US Patent 11558223 Adaptive receiver with pre-cursor cancelation
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US Patent 11646756 Determining sampling thresholds of SERDES receivers
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US Patent 11658648 Variation tolerant linear phase-interpolator
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Patent Inventor Names
Yasuo Hidaka
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Junqing (Phil) Sun
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10892763
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Patent Primary Examiner
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James M Perez
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