Patent attributes
A three-dimensional semiconductor device includes a stacked structure on a lower structure, the stacked structure including a lower group including gate electrodes vertically stacked and spaced apart from each other, and an upper group including gate electrodes vertically stacked and spaced apart, the lower group and the upper group being vertically stacked, and a vertical structure passing through the stacked structure. The vertical structure may include a vertical core pattern, a vertical buffer portion therein, and a surrounding vertical semiconductor layer, the vertical structure may include a lower vertical portion passing through the lower group and an upper vertical portion passing through the upper group, an upper region of the lower vertical portion may have a width greater than that of a lower region of the upper vertical portion. The vertical buffer portion may be in the lower vertical portion and below the upper vertical portion.
