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US Patent 10943830 Self-aligned structure for semiconductor devices
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Patent
Date Filed
October 4, 2017
Date of Patent
March 9, 2021
Patent Application Number
15724411
Patent Citations
US Patent 10141296 Dummy fin cell placement in an integrated circuit layout
US Patent 10170583 Forming a gate contact in the active area
US Patent 10204202 Dummy fin cell placement in an integrated circuit layout
US Patent 10249605 Integrated circuit devices
US Patent 10304844 Stacked FinFET EEPROM
US Patent 10304946 Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices
US Patent 10374083 Vertical fin field effect transistor with reduced gate length variations
US Patent 10347751 Self-aligned epitaxy layer
US Patent 10607890 Selective removal of semiconductor fins
US Patent 10403714 Fill fins for semiconductor devices
•••
Patent Citations Received
US Patent 12119259 Transistor gate contacts and methods of forming the same
0
US Patent 11764259 Vertical field-effect transistor with dielectric fin extension
US Patent 11393713 Semiconductor device and manufacturing method therefore
US Patent 11557650 Semiconductor device and manufacturing method thereof
US Patent 11276651 IC product comprising a single active fin FinFET device and an electrically inactive fin stress reduction structure
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10943830
Patent Primary Examiner
David E. Graybill
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