US Patent 10949096 Method using logical based addressing for latency reduction
Patent 10949096 was granted and assigned to Western Digital on March, 2021 by the United States Patent and Trademark Office.
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Patent abstract
A method for control of latency information through logical block addressing is described comprising receiving a computer command, performing a read flow operation on a computer buffer memory based on the computer command; populating at least one metadata frame with data based on logical block address latency information; initiating a serial attached data path transfer for one of transmitting and receiving data to the computer drive and transmitting data to a host based on the second latency.
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Patent Inventor Names
Darin Edward Gerhart0
Mark David Erickson0
Nicholas Edward Ortmeier0
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US Patent 10949096 Method using logical based addressing for latency reduction
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Patent applicant
Current assignee
Patent jurisdiction
Patent number
10949096
Date of patent
March 16, 2021
Patent application number
16597709
Date Filed
October 9, 2019
Patent citations
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