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US Patent 10951216 Synchronization of clock signals generated using output dividers

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
October 14, 2019
Date of Patent
March 16, 2021
Patent Application Number
16600793
Patent Citations
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US Patent 10320509 Fail safe clock buffer and clock generator
Patent Citations Received
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US Patent 11496234 Synchronizing update of time of day counters using time stamp exchange over a control plane
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US Patent 11502764 FSYNC mismatch tracking
0
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US Patent 11502812 Data protocol over clock line
0
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US Patent 11526193 Maintaining the correct time when counter values are transferred between clock domains
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US Patent 11671238 Secondary phase compensation assist for PLL IO delay
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US Patent 11777703 Phase transport with frequency translation without a PLL
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US Patent 11863299 Shared communication channel that interleaves 1 PPS signals and messaging
0
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US Patent 11876607 FSYNC mismatch tracking
0
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US Patent 11994896 Maintaining the correct time when counter values are transferred between clock domains
0
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US Patent 12021960 Maintaining a virtual time of day
0
•••
Patent Inventor Names
Xue-Mei Gong
0
James D. Barnette
0
William Anker
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10951216
Patent Primary Examiner
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Sibin Chen

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