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US Patent 10996959 Hybrid processor

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US Patent 12061969 System and method for energy-efficient implementation of neural networks
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US Patent 11941405 Computational memory
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Patent abstract

A hybrid computer that comprises a sequential processor, a single instruction massively parallel (SIMD) processor, and shared memory module that is shared between the sequential processor and the SIMD processor.

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Patent Inventor Names
Amir Morad0
Leonid Yavits0
Ran Ginosar0
Shahar Kvatinsky0
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US Patent 11763186 Reducing parasitic interactions in a qubit grid for surface code error correction
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US Patent 11694104 Reducing parasitic interactions in a qubit grid
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US Patent 11687820 Frequency pattern for reducing parasitic interactions in a qubit grid
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Edits on 24 May, 2023
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edited on 24 May, 2023
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=109969590
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Infobox
Is a
Patent
Patent
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
109969590
Date of Patent
May 4, 2021
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Patent Application Number
149898800
Date Filed
January 7, 2016
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=109969590
Patent Citations Received
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US Patent 11500811 Apparatuses and methods for map reduce
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US Patent 11562280 Reducing parasitic interactions in a qubit grid for surface code error correction
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Patent Primary Examiner
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Mark A Giardino, Jr.
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Edits on 22 Mar, 2023
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US Patent 11562280 Reducing parasitic interactions in a qubit grid for surface code error correction
0
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US Patent 11500811 Apparatuses and methods for map reduce
0
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Website URL
https://pdfpiw.uspto.gov/.piw?Docid=10996959
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 US Patent 10996959 Hybrid processor

Infobox
Is a
Patent
Patent
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
10996959
Date of patent
May 4, 2021
Patent application number
14989880
Date Filed
January 7, 2016
Patent primary examiner
‌
Mark A Giardino, Jr.

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