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US Patent 10996959 Hybrid processor
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Patent
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Date Filed
January 7, 2016
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Date of Patent
May 4, 2021
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Patent Application Number
14989880
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Patent Citations Received
US Patent 12061969 System and method for energy-efficient implementation of neural networks
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US Patent 11562280 Reducing parasitic interactions in a qubit grid for surface code error correction
US Patent 11687820 Frequency pattern for reducing parasitic interactions in a qubit grid
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US Patent 11694104 Reducing parasitic interactions in a qubit grid
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US Patent 11763186 Reducing parasitic interactions in a qubit grid for surface code error correction
US Patent 11941405 Computational memory
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US Patent 11500811 Apparatuses and methods for map reduce
Patent Inventor Names
Leonid Yavits
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Ran Ginosar
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Shahar Kvatinsky
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Amir Morad
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
10996959
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Patent Primary Examiner
Mark A Giardino, Jr.
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