Patent 11005644 was granted and assigned to Arista Networks on May, 2021 by the United States Patent and Trademark Office.
Embodiments of the present disclosure include techniques for generating accurate time stamps. In one embodiment, a first timing reference signal corresponding to a first clock domain is combined with a first clock signal corresponding to a second clock domain to produce a second timing reference signal that includes quantization noise. The second timing reference signal is filtered to remove the quantization noise and generate a filtered timing reference signal. The filtered timing reference signal may be sampled in the second clock domain to obtain a time stamp. In one embodiment, a phase locked loop (PLL) is used as the filter. The PLL may generate first and second ramps that correspond to time. One of the ramps may be sampled to obtain a time stamp, for example.