Patent attributes
The present invention provides 3D stack NOR devices having increased storage area. In one aspect, a method of forming a memory device includes: forming a memory stack on a wafer having alternating sacrificial word and bit line layers separated by dielectric layers; patterning a channel hole in the stack; recessing the sacrificial word line layers to form divots along opposite sides of the channel hole; selectively forming a floating gate stack in the divots; filling the channel hole and divots to form a channel; patterning the memory stack into a stair case structure; burying the memory stack in a dielectric; replacing the sacrificial word line layers in the memory stack with word line contacts; and replacing the sacrificial bit line layers in the memory stack with bit line contacts. A memory device is also provided.
