Patent attributes
A memory device includes a stacked structure including conductive layers and first insulating layers alternately stacked along a first direction; a first array region; a second array region; and a connection region disposed between the first array region and the second array region, and including a staircase region, an unprocessed region, a bottom isolating member and a common wall, wherein the unprocessed region extends along the first direction and has an isolating sidewall, the isolating sidewall electrically isolates the conductive layers from the unprocessed region, the staircase region is adjacent to a first side of the unprocessed region, and the common wall is adjacent to a second side of the unprocessed region. A portion of the conductive layers continuously extends in the staircase region, the first array region, the common wall and the second array region.
