Patent attributes
A clock data recovery circuit includes a circuit that receives a data signal for which each of a plurality of potential levels is associated with a value of 2 bits or more, based on a result of a first comparison that compares the 3 or more first thresholds with the data signal at timing synchronized with a clock signal; a circuit that outputs a result of a second comparison that compares the data signal with a second threshold at the timing; a circuit that generates a phase difference signal indicating whether to advance or delay a phase of the clock signal, based on the result of the determination and the result of the second comparison; a filter that generates a phase adjusted value indicating an adjustment amount of the phase, based on the phase difference signal; and a circuit that adjusts the phase based on the phase adjusted value.
