US Patent 11171076 Compute-in-memory packages and methods forming the same

A method includes placing a first plurality of dies over a carrier. The first plurality of dies include at least a first logic die and a first memory die, placing a second plurality of dies over the first plurality of dies. The second plurality of dies are electrically coupled to the first plurality of dies, and include at least a second logic die and a second memory die. A third plurality of dies are placed over the second plurality of dies, and are electrically coupled to the first plurality of dies and the second plurality of dies. The third plurality of dies include at least a third logic die and a third memory die. The method further includes forming electrical connectors over and electrically coupling to the first plurality of dies, the second plurality of dies, and the third plurality of dies.