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US Patent 11237880 Dataflow all-reduce for reconfigurable processor systems

Patent 11237880 was granted and assigned to SambaNova Systems on February, 2022 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Patent Applicant
SambaNova Systems
SambaNova Systems
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Current Assignee
SambaNova Systems
SambaNova Systems
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
112378800
Patent Inventor Names
Bandish B. Shah0
Gregory Frederick Grohoski0
Kin Hing Leung0
Martin Russell Raumann0
Qi Zheng0
Ravinder Kumar0
Sumti Jairath0
Date of Patent
February 1, 2022
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Patent Application Number
173799240
Date Filed
July 19, 2021
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Patent Citations
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US Patent 10621138 Network communications using pooled memory in rack-scale architecture
Patent Citations Received
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US Patent 12008417 Interconnect-based resource allocation for reconfigurable processors
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US Patent 11625284 Inter-node execution of configuration files on reconfigurable processors using smart network interface controller (smartnic) buffers
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US Patent 11609798 Runtime execution of configuration files on reconfigurable processors with varying configuration granularity
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US Patent 11782760 Time-multiplexed use of reconfigurable hardware
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US Patent 11917000 Message queue routing system
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US Patent 11886930 Runtime execution of functions across reconfigurable processor
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US Patent 11886931 Inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers
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...
Patent Primary Examiner
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Hiren P Patel
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Patent abstract

Roughly described, a system for data parallel training of a neural network on multiple reconfigurable units configured by a host with dataflow pipelines to perform different steps in the training CGRA units are configured to evaluate first and second sequential sections of neural network layers based on a respective subset of training data, and to back-propagate the error through the sections to calculate parameter gradients for the respective subset. Gradient synchronization and reduction are performed by one or more units having finer grain reconfigurability, such as an FPGA. The FPGA performs synchronization and reduction of the gradients for the second section while the CGRA units perform back-propagation through the first sequential section. Intermediate results are transmitted using a P2P message passing protocol layer. Execution of dataflow segments in the different units is triggered by receipt of data, rather than by a command from any host system.

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