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US Patent 11886930 Runtime execution of functions across reconfigurable processor

Patent 11886930 was granted and assigned to SambaNova Systems on January, 2024 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Patent Applicant
SambaNova Systems
SambaNova Systems
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Current Assignee
SambaNova Systems
SambaNova Systems
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
118869300
Patent Inventor Names
Ranen Chatterjee0
Bandish B. Shah0
Arnav Goel0
Sumti Jairath0
Manish K. Shah0
Emre Ali Burhan0
Ram Sivaramakrishnan0
Kin Hing Leung0
...
Date of Patent
January 30, 2024
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Patent Application Number
175226720
Date Filed
November 9, 2021
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Patent Citations
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US Patent 11080227 Compiler flow logic for reconfigurable architectures
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US Patent 11182264 Intra-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS)
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US Patent 11184439 Communication with accelerator via RDMA-based network adapter
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US Patent 11237880 Dataflow all-reduce for reconfigurable processor systems
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US Patent 11392740 Dataflow function offload to reconfigurable processors
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US Patent 11625283 Inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers
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US Patent 11687264 Technologies for accelerator interface
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US Patent 11625284 Inter-node execution of configuration files on reconfigurable processors using smart network interface controller (smartnic) buffers
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Patent Primary Examiner
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Hiren P Patel
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Patent abstract

The technology disclosed relates to runtime execution of functions across reconfigurable processor. In particular, the technology disclosed relates to a runtime logic that is configured to execute a first set of functions in a plurality of functions and/or data therefor on a first reconfigurable processor, and a second set of functions in the plurality of functions and/or data therefor on additional reconfigurable processors. Functions in the second set of functions and/or the data therefor are transmitted to the additional reconfigurable processors using one or more of a first reconfigurable processor-to-additional reconfigurable processors buffers, and results of executing the functions and/or the data therefor on the additional reconfigurable processors are transmitted to the first reconfigurable processor using one or more of additional reconfigurable processors-to-first reconfigurable processor buffers.

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