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US Patent 11282829 Integrated circuit with mixed row heights

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
May 26, 2020
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Date of Patent
March 22, 2022
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Patent Application Number
16883740
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Patent Citations Received
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US Patent 11640959 Semiconductor device
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US Patent 11699015 Circuit arrangements having reduced dependency on layout environment
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US Patent 11709985 Semiconductor device including standard cells with combined active region
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US Patent 11803683 Method of and system for manufacturing semiconductor device
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US Patent 11803682 Semiconductor device including standard cell having split portions
Patent Inventor Names
Kam-Tou Sio
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Chung-Hsing Wang
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Jiann-Tyng Tzeng
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Yi-Kan Cheng
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11282829
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Patent Primary Examiner
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Fernando L Toledo
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CPC Code
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H01L 27/11807
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H01L 2027/11855
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G06F 30/30
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G06F 2111/04
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G06F 2111/20
0
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H01L 27/0207
0
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H01L 29/785
0

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