US Patent 11283459 Calibration of a time-to-digital converter using a virtual phase-locked loop

In at least one embodiment, a method includes generating a digital time code corresponding to an input clock signal using a time-to-digital converter responsive to a reference clock signal and a time-to-digital converter calibration signal. The method includes generating the time-to-digital converter calibration signal based on the digital time code. Generating the time-to-digital converter calibration signal includes generating a digital error signal based on the digital time code and an estimated digital time code, and adapting the time-to-digital converter calibration signal based on the digital error signal.