US Patent 11923857 DTC nonlinearity correction

Embodiments herein describe correcting nonlinearity in a Digital-to-Time Converter (DTC) by relaxing a DTC linearity requirement, which results in the correction being co-adapted with a DTC gain calibration loop which can operate in parallel with a DTC integral nonlinearity (INL) correction loop. In one embodiment, the DTC gain calibration loop and the DTC INL correction loop are constrained when determining a nonlinearity correction code to improve the likelihood they converge. Once determined, the nonlinearity correction code can be combined with an digital code output by a time-to-digital converter (TDC) to generate a phase difference between a reference clock and a feedback clock.