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US Patent 11289584 Inner spacer features for multi-gate transistors
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Patent
Date Filed
July 23, 2020
Date of Patent
March 29, 2022
Patent Application Number
16937164
Patent Citations
US Patent 10199502 Structure of S/D contact and method of making same
US Patent 10290546 Threshold voltage adjustment for a gate-all-around semiconductor structure
US Patent 10032627 Method for forming stacked nanowire transistors
US Patent 10109721 Horizontal gate-all-around device having wrapped-around source and drain
US Patent 10157799 Multi-gate device and method of fabrication thereof
US Patent 10475902 Spacers for nanowire-based integrated circuit device and method of fabricating same
Patent Citations Received
US Patent 12087842 Inner spacer features for multi-gate transistors
0
US Patent 11682714 Inner spacer features for multi-gate transistors
0
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
11289584
Patent Primary Examiner
David C Spalla
CPC Code
H01L 29/42392
H01L 29/66439
H01L 29/6653
H01L 29/6656
H01L 29/66553
H01L 29/66795
H01L 29/6681
H01L 29/775
H01L 29/785
H01L 29/7851
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