Patent attributes
A system and method for providing electrical circuit design using cells with metal lines are described herein. According to one embodiment, a method includes instantiating a first parameterized cell (PCELL) into a first region of a row of an electrical circuit design. The first PCELL includes field effect transistor (FET) data representing a FET structure having a horizontal dimension and first metal track data representing a first set of adjustable parallel metal line segments extending along the horizontal dimension of the FET structure. The method also includes instantiating a second PCELL into a second region of the row adjacent to the first region. The second PCELL includes second metal track data representing a second set of adjustable parallel metal line segments. The method further includes connecting the first set of adjustable parallel metal line segments to the second set of adjustable parallel metal line segments and eliminating a connectivity short.
