Patent attributes
A non-volatile memory device includes a first semiconductor layer having a stair area and a cell area having a memory cell array formed therein, and a second semiconductor layer including a page buffer connected to the memory cell array. The first semiconductor layer includes a plurality of word lines, a ground selection line in a layer on the word lines, a common source line in a layer on the ground selection line, a plurality of vertical pass transistors in the stair area, and a plurality of driving signal lines in the same layer as the common source line. The word lines form a stair shape in the stair area, and each of the vertical pass transistors is connected between a corresponding one of the word lines and a corresponding one of the driving signal lines.
