Patent attributes
A semiconductor device includes a plurality of cell gate electrodes on a semiconductor substrate. End portions of the cell gate electrodes include stepped-pad regions that extend in a direction parallel to a surface of the semiconductor substrate. Vertical structures are on the semiconductor substrate and pass through the plurality of cell gate electrodes. The vertical structures respectively include a channel layer. Upper peripheral transistors are disposed on the semiconductor substrate. The upper peripheral transistors include an upper peripheral gate electrode at a level higher than a level of the plurality of cell gate electrodes, body patterns passing through the upper peripheral gate electrode and electrically connected to the pad regions, and gate dielectric layers between the upper peripheral gate electrode and the body patterns.