US Patent 11430802 Nonvolatile memory device including erase transistors

A nonvolatile memory device includes bitlines, a source line, cell channel structures, a gate electrode structure, erase channel structures and an erase selection line. The bitlines are disposed at a first end portion of a cell region, arranged in a first horizontal direction and extend in a second horizontal direction. The source line is disposed at a second end portion of the cell region and extend in the second horizontal direction. The cell channel structures are disposed in a cell string area of the cell region and are respectively connected between the bitlines and the source line. The erase channel structures are disposed in a contact area of the cell region and respectively connected between the bitlines and the source line. The erase channel structures include erase transistors. The erase selection line is disposed in the contact area to form a gate electrode of the erase transistors.