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US Patent 11374118 Method to form a 3D integrated circuit
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Patent
Date Filed
July 22, 2020
Date of Patent
June 28, 2022
Patent Application Number
16936352
Patent Citations
US Patent 10199354 Die sidewall interconnects for 3D chip assemblies
Patent Citations Received
US Patent 11967583 3D semiconductor device and structure with metal layers
0
Patent Inventor Names
Zeev Wurman
0
Deepak C. Sekar
0
Zvi Or-Bach
0
Brian Cronquist
0
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
11374118
Patent Primary Examiner
Alexander O Williams
CPC Code
H01L 27/0688
H01L 25/167
H01L 21/76898
H01L 21/823475
H01L 24/08
H01L 21/823871
H01L 27/11551
H01L 29/66901
H01L 27/0207
H01L 27/11898
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