US Patent 11379388 Credit scheme for multi-queue memory controllers

A memory controller includes an address decoder, a first command queue coupled to a first output of the address decoder for receiving memory access requests for a first memory channel, and the second command queue coupled to a second output of the address decoder for receiving memory access requests for a second memory channel. A request credit control circuit is coupled to the first command queue and the second command queue, and operates to track a number of outstanding request credits. The request credit control circuit issues a request credit in response to a designated event based on a number of available entries of the first and second command queues.